module EXMEM(
    input clk, rst, 

    input EX_RegW, 
    output reg MEM_RegW, 

    input [1:0] EX_Mem2R, 
    output reg [1:0] MEM_Mem2R, 

    input EX_Branch, 
    output reg MEM_Branch, 

    input EX_MemR, 
    output reg MEM_MemR,

    input EX_MemW, 
    output reg MEM_MemW, 

    input [4:0] gprWeSel, 
    output reg [4:0] MEM_gprWeSel, 

    input [31:0] aluDataIn2_fwB, 
    output reg [31:0] MEM_aluDataIn2_fwB, 

    input [31:0] aluDataOut, 
    output reg [31:0] MEM_aluDataOut, 

    input [31:0] EX_PC, 
    output reg [31:0] MEM_PC
);

    always @(posedge clk, posedge rst)
    begin
        if (rst)
        begin
            MEM_aluDataOut = 0;
            MEM_Branch = 0;
            MEM_gprWeSel = 0;
            MEM_Mem2R = 0;
            MEM_MemR = 0;
            MEM_MemW = 0;
            MEM_aluDataIn2_fwB = 0;
            MEM_RegW = 0;
            MEM_PC = 0;
        end

        else
        begin
            MEM_aluDataOut = aluDataOut;
            MEM_Branch = EX_Branch;
            MEM_gprWeSel = gprWeSel;
            MEM_Mem2R = EX_Mem2R;
            MEM_MemR = EX_MemR;
            MEM_MemW = EX_MemW;
            MEM_aluDataIn2_fwB = aluDataIn2_fwB;
            MEM_RegW = EX_RegW;
            MEM_PC = EX_PC;
        end
    end

endmodule